Karthik Vippala
12.6K subscribers
2:36
Operations in sensitivity lists !! always @(a && b) .....
Karthik Vippala
884 views • 1 year ago
6:45
Fixded Priority Arbitration | Efficient way to CODE RTL #2 #vlsi
Karthik Vippala
2.1K views • 1 year ago
3:33
What is the difference between 1 and 1'b1 in Verilog ? || Concatenation Problems { }
Karthik Vippala
1.9K views • 1 year ago
3:53
What is Reverse Case Statement in Verilog? Case(1'b1)
Karthik Vippala
3.6K views • 1 year ago
7:15
Strict Priority Arbitration (Design, Testbench, Assertions) CODERTL#1
Karthik Vippala
1.9K views • 2 years ago
6:46
X-propagation in SOC design flow | Do you Love your X !!
Karthik Vippala
4.9K views • 2 years ago
3:04
A Google Interview Question. # Digital Design
Karthik Vippala
4.9K views • 2 years ago
6:48
How to design Clock Divided By 4.5 ? Explained!
Karthik Vippala
12K views • 2 years ago
6:12
Downloading & Installation of Intel Quartus Prime & ModelSim [2022]
Karthik Vippala
17K views • 2 years ago
4:22
How to swap data of registers using Logic gates? 🤔Brain Teaser #3
Karthik Vippala
2.1K views • 2 years ago
26:43
What should I learn ,to be good at physical design ? 🤔💭 | A-Z of Physical Design with Nikhil Shah.
Karthik Vippala
1.3K views • 2 years ago
22:18
In Talk With Expert : NIKHIL SHAH | Part -1 | Will AI Impact VLSI ? 🤔
Karthik Vippala
1.8K views • 2 years ago
5:05
How to count number of one's in a binary vector using adders?🤔💭 Brain Teaser#2
Karthik Vippala
6.8K views • 3 years ago
7:21
What is Dual Edge Triggered Flip Flop? How to design it?🤔 Explained 👍
Karthik Vippala
8.2K views • 3 years ago
5:46
This Will Change How YOU Think of Digital Design 🤔| BCD Multiplier | Brain Teaser#1
Karthik Vippala
1.7K views • 3 years ago
5:52
How to implement Logic Gates & Boolean expression using a switches? || Switching Theory||
Karthik Vippala
3.2K views • 3 years ago
6:05
Signal Synchronization Rules (Must Follow!!)
Karthik Vippala
8.4K views • 3 years ago
6:31
Icarus verilog + GTKWave installing and running | Free software for verilog HDL
Karthik Vippala
88K views • 3 years ago
11:03
Which to use , Asynchronous reset or synchronous reset ? Resets Explained || Reset synchronizer!!
Karthik Vippala
25K views • 3 years ago
10:00
How to represent Decimal Number in IEEE 754 (Single Precision)? In 4 steps !! Why do we use bias ?
Karthik Vippala
5.8K views • 3 years ago
13:01
11011 Sequence detector (5 bits) using Moore Overlap & Non-Overlap *Simplified*
Karthik Vippala
28K views • 3 years ago
7:17
IMPLY Gate || what is meant by Functionally Complete? Is IMPLY Gate Functionally Complete?
Karthik Vippala
2.8K views • 3 years ago
15:20
11011 sequence detector (5bits) using Melay Overlap & Non-overlap || *simple trick*
Karthik Vippala
41K views • 4 years ago
1:51
What is difference between PARAMETER and ARGUMENT ? #In2min
Karthik Vippala
8.7K views • 4 years ago
10:10
One hot vs binary encoding || which one is better for FPGA/ASIC? || Explained with example
Karthik Vippala
13K views • 4 years ago
12:38
How to design self correcting Johnson's Counter? *Simplified*
Karthik Vippala
7.2K views • 4 years ago
3:15
What is Round Robin Arbitration ? Explained
Karthik Vippala
9.5K views • 4 years ago
13:14
How to multiply signed binary number ? Using Booth's Algorithm || simplified
Karthik Vippala
8.2K views • 4 years ago
5:17
Mux synchronizer (Clock domain crossing)
Karthik Vippala
17K views • 4 years ago
9:38
What are special number systems? Explained with examples!!
Karthik Vippala
1.4K views • 4 years ago
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