03:The 6502 is a CISC 8 bit CPU. We'll be implementing it as a synchronous bus FPGA module. It was widely successful, including two implementations by this very project.

And yet, I'm rebuilding it. In fact, I'm fitting a whole new architecture to it. Why?

I'd like to thank my Patreon BBC Micro level supporter, Yehuda T. Deutsch.
You, too, can support my work on Patreon:   / compusar  

Discord server invite:   / discord  

The code is available at https://github.com/CompuSAR/sar6502-sync
6502 block diagram is at https://www.witwright.com/DonPub/6502...

Table of contents:
00:00 - Rewriting the 6502, again
01:42 - Synchronous vs. Asynchronous bus
03:59 - Needs too slow a clock
04:46 - Should need too many cycles/cycle
07:21 - Constant cycles/cycle implementation
08:50 - Clock speed keeps changing
10:22 - Variable cycles/cycle implementation
12:03 - Moderator implementation
15:04 - Other advantages