Chapters in this Video:
00:00 Introduction
00:35 Contents
01:48 Basics of Seven segments
06:16 Hex to Seven segment
9:50 Seven segment on Nexys 4 (FPGA) Board
12:50 Verilog Code of Seven Segment interfacing with switches
18:03 Nexys 4 Board Reference manual
18:54 How to make new project in Vivado
20:11 Add verilog file and pin mapping in vivado
27:41 Synthesis, Implementation and Bit file generation
30:06 Downloading the bit file on FPGA Board
31:42 Testing on hardware (FPGA) Board

The Nexys4 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7 Field Programmable
Gate Array (FPGA) from Xilinx.
The Nexys4 board contains two four-digit common anode seven-segment LED displays.

In this video, we will learn how to interface these 7 segments with the switches available on FPGA board.
This video consists of following sections:

Introduction
Basics of Seven segments
Seven segment on Nexys 4 (FPGA) Board
Verilog Code of Seven Segment interfacing with switches
Make new project in Vivado
Input output pin mapping in vivado
Bit file generation
Downloading the bit file on FPGA Board
Testing on hardware (FPGA) Board

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The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the
LED cathodes remain separate. The common anode signals are available as eight “digit enable”
input signals to the 8-digit display.

The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG (so, for example, the eight “D” cathodes from the eight digits are grouped
together into a single circuit node called “CD”).
These seven cathode signals are available as inputs to the 8-digit
display.
This signal connection scheme creates a multiplexed display, where the cathode signals are common to all
digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted.

To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the
Nexys4 uses transistors to drive enough current into the common anode point, the anode enables are inverted.
Therefore, both the AN0..7 and the CA..G/DP signals are driven low when active.
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#fpga
#verilog
#vhdl
#vivado
#xilinx
#decoder
#intellcity